Semiconductor logic circuit devices are shipped through three steps, i.e., a design step, a production step and a test step. In a test step, a test vector is applied to a manufactured semiconductor logic circuit device, to observe a test response from the semiconductor logic circuit device, and to compare the test response with an expected test response, thus determining whether the semiconductor logic circuit device is good or defective. The rate of good semiconductor logic circuit devices is called a manufacturing yield which would remarkably affect the semiconductor logic circuit devices in manufacturing cost.
Generally, a semiconductor logic circuit device (mainly, a sequential circuit) is constructed by a combinational portion formed by logic elements such as AND gates, NAND gates, OR gates and NOR gates, and a flip-flop group storing an internal state of the circuit. In this case, the combinational portion has external input lines PI, pseudo external input lines PPI serving as output lines of the flip-flop group, external output lines PO and pseudo external output lines PPO serving as input lines of the flip-flops. That is, inputs to the combinational portion are ones supplied directly from the external input lines and ones supplied by the pseudo external input lines. Also, outputs from the combinational portion are ones appearing directly at the external output lines and ones appearing at the pseudo external output lines.
In order to test the combinational portion of a semiconductor logic circuit device, a predetermined test vector is required to be applied thereto from the external input lines and the pseudo external input lines of the combinational portion, and a test response is required to be observed from the external output lines and the pseudo external output lines of the combinational portion. Here, one test vector is formed by bits corresponding to the external input lines and the pseudo external input lines. Also, one test response is formed by bits corresponding to the external output lines and the pseudo external output lines.
However, it is generally impossible to directly access the output lines of the flip-flops (the pseudo external input lines) and the input lines of the flip-flops (the pseudo external output lines) in the semiconductor logic circuit device from the exterior. Therefore, in order to test the combinational portion, there are problems in the controllability of the pseudo external input lines and the observability of the pseudo external output lines.
A scan design is a technique for solving the problems of controllability and observability in the test of the combinational portion. Such a scan design replaces the flip-flops (FF) with scan flip-flops (scan FFs) by which one or a plurality of scan chains are formed. The scan flip-flops are controlled by a scan enable signal SE. For example, when SE=0, the scan flip-flops perform the same operation as conventional flip-flops. That is, if a clock pulse is given, the output values of the scan flip-flops are renewed by the combinational portion. On the other hand, when SE=1, the scan flip-flops with the other scan flip-flops within the same scan chain form one shift register. That is, if a clock pulse is given, new values are shifted from the exterior in the scan flip-flops, and simultaneously, values which have been in the scan flip-flops are shifted out to the exterior. Generally, scan flip-flops in the same scan chain share the same scan enable signal SE; however, scan enable signals SE in different scan chains may be the same or different from each other.
FIG. 14 is a circuit diagram for explaining a real speed scan test targeting a delay fault of a combination portion of a scan-designed semiconductor logic circuit device. In FIG. 14, reference numeral 1 designates a semiconductor logic circuit device, and 2 designates a tester.
The semiconductor logic circuit device of FIG. 14 is constructed by a combinational portion 11 formed by logic elements such as AND gates, OR gates, NAND gates, and NOR gates, a flip-flop group 12, a phase-locked loop (PLL) circuit 13 for generating a high-speed clock signal RCLK, and a multiplexer 14 for selecting the real speed clock signal RCLK or a low-speed shift clock signal SCLK supplied from the tester 2 and supplying the selected clock signal to the scan flip-flop group 12. Note that a clock enable signal CE is used for controlling generation of capture pulses from the PLL circuit 13.
The combinational portion 11 has external input lines PI, pseudo external input lines PPI serving as output lines of the scan flip-flop group 12, external output lines PO, and pseudo external output lines PPO serving as input lines of the scan flip-flop group 12. Note that the number of the external input lines PI is not always the same as that of the external output lines PO; however, the number of the pseudo external input lines PPI is always the same as that of the pseudo external output lines PPO.
FIG. 15 is a timing diagram for explaining the real speed scan test of FIG. 14. A real speed scan test is performed by repeating shift operations and two capture operations (hereinafter, referred to as a double-capture operation). The shift operation is performed by a shift mode where a scan enable signal SE is “1”. In the shift mode, one or plural low-speed shift clock signals S1, . . . , SL are given so that one or a plurality of new values are shifted in the scan flip-flop group 12 within a scan chain. Simultaneously, one or a plurality of current values in the scan flip-flop group 12 within the scan chain are shifted out to the exterior. Note that a maximum value L is the number of scan flip-flops of the scan flip-flop group 12. Also, even if the shift clock pulses are at a low speed, no problem occurs. On the other hand, the capture operation is performed by a capture mode where the scan enable signal SE is “0”. In the shift mode, a clock signal CE is enabled (CE=“0”), so that two clock pulses C1 and C2 in response to rising edges of the clock enable signal CE are supplied from the PLL circuit 13 of FIG. 14 to the scan flip-flop group 12 in the one scan chain. Thus, the values at the pseudo external output lines PPO of the combinational portion 11 are taken into all the scan flip-flops of the scan flip-flop group 12. Since the interval T2 of these clock pulses C1 and C2 is determined in accordance with a design specification, the effect of the real speed scan test can be obtained.
A shift operation is used for applying a test vector to the combinational portion 11 through the pseudo external input lines PPI and for observing a test vector from the combinational portion 11 through the pseudo external output lines PPO. Also, a capture operation is used for obtaining a test response of the combinational portion 11 in the scan flip-flop group 12. Shift operations and double-capture operations are repeated upon all test vectors, thus real-speed scan-testing the combinational portion 11. Such a test system is called a real-speed scan test system.
In a real speed scan test, application of a test vector to the combinational portion 11 is formed by a portion applied directly from the exterior input lines PI and a portion applied by shift operations. Since an arbitrary logic value is set in an arbitrary scan flip-flop, the problem of controllability of the pseudo external input lines PPI is solved. On the other hand, observation of a test response from the combinational portion 11 is formed by a portion performed directly from the external output lines PO and a portion performed by shift operations. Since an output value of an arbitrary scan flip-flop can be observed by shift operations, the problem of observability of the pseudo external input lines PPI is solved. Thus, in a real-speed scan test system, it is only necessary to obtain a test vector and an expected test response for the combinational portion 11 by using an automatic test pattern generation (ATPG) program.
Despite the effectiveness of the above-mentioned real speed scan test system, there is a problem in that the power consumption is remarkably larger in a test mode than in a usual operation mode. For example, if the semiconductor logic circuit device is constructed by CMOS circuits, the power consumption consists of static power consumption due to leakage currents and dynamic power consumption due to switching operations of the logic gates and the flip-flops. Additionally, the latter dynamic power consumption consists of shift power consumption in shift operations and capture power consumption in capture operations.
Generally, a large number of clock pulses are required for one test vector in shift operations. For example, in order to set new values in all the scan flip-flops of the scan flip-flop group 12 of a scan chain, a number of clock pulses corresponding to the number of the scan flip-flops are required at most. As a result, the shift power consumption is increased to induce excessive heat. Therefore, semiconductor logic circuit devices would be damaged. Various techniques for decreasing the shift power consumption have been vigorously developed.
On the other hand, generally, two clock pulses per one scan chain are required for one test vector in a double-capture operation. Therefore, heat by the double-capture operation mode creates no problem. However, in a capture mode, when a test response of the combinational portion 11 appearing at the pseudo external output lines PPO is obtained in the scan flip-flop group 12, if the values of the test response are different from the current values of the scan flip-flop group 12, the values of the corresponding scan flip-flop group 12 change. If the number of the scan flip-flop group 12 whose output values have changed, the power supply voltage is instantaneously changed by the switching operation of the logic gates and the scan flip-flops 12. This is also called an IR (I: current and R: resistance) drop phenomenon. The IR drop phenomenon would erroneously operate the circuit resulting in erroneous test response values in the scan flip-flop group 12. Thus, even semiconductor logic circuit devices normally operable in a usual state would be deemed to be defective in a test state, which can be an erroneous test. As a result, the manufacturing yield would be decreased. Particularly, when semiconductor logic circuit devices become ultra-large in scale, more fine-structured and lower in power supply voltage, the manufacturing yield caused by the erroneous test would be remarkably decreased. Therefore, it is essential to decrease the capture power consumption in a double-capture operation for a real speed test.
The capture power consumption can be decreased by a clock gating technique; however, this would remarkably affect the physical design of semiconductor logic circuit devices. Also, the capture power consumption can be decreased by a one hot technique or a multiple clock technique; however, the former technique would remarkably increase test data amount, and the latter technique would require enormous memory consumption in generating test vectors, which is a shortcoming. Therefore, in view of the decrease of the capture power consumption, it is expected to decrease the impact to the physical design, to suppress the increase of test data amount and to decrease the required memory amount.
On the other hand, many test cubes, i.e., input vectors with don't-care bits (hereinafter, referred to as X-bits) are usually generated in a process for generating test vectors using an ATPG program. Also, when a set of test vectors without X-bits are given, some bits of some test vectors can be converted into X-bits without changing the fault detection rate of the set of test vectors. That is, test cubes can be obtained by an X-bit extracting program. The reason for the existence of test cubes is mainly to have only to set necessary logic values in a part of bits of the external input lines PI and the pseudo external input lines PPI in order to detect one target fault in the combinational portion 11. Since assignment of 0's or 1's to the remainder bits does not affect the detection of the target fault, such remainder bits are X-bits for the target fault.
A test cube with X-bits is strictly an intermediate product appearing in a process for generating a test cube without X-bits. Therefore, 0 or 1 finally have to be filled into the X-bits of the test cube by an appropriate method, i.e., an algorithm filling method, a merge filling method or a random filling method.
The algorithm filling method determines and fills optimum logic values (0 or 1) for the X-bits in a test cube in an algorithm in order to obtain an object. Such an algorithm is often included on an ATPG program. This algorithm filling method is used for decreasing the total number of test vectors in dynamic compaction (see: non-patent documents 1 and 2), for decreasing the shift power consumption (see: non-patent document 3) or for decreasing the capture power consumption in a single-capture operation (see: non-patent document 4).
When a test cube is merged with another test cube, the merge filling method fills 0 or 1 in X-bits of the test cubes so that a bit of the test cube has the same logic value as its corresponding bit of the other test cube. For example, in order to merge a test cube 1X0 with a test cube 11x, 1 is assigned to the X-bit of the test cube 1X0 and 0 is assigned to the X-bit of the test cube 11x. This merge filling method is used for decreasing the total number of test vectors in static compaction (see: non-patent document 1) or for decreasing the shift power consumption (see: non-patent document 5).
The random filling method assigns 0 or 1 randomly to X-bits in a test cube. This random filling method is often performed for remaining X-bits after the algorithm filling method or the merge filling method is performed. This random filling method is used for decreasing the total number of test vectors in dynamic compaction (see: non-patent document 1) or for decreasing the shift power consumption (see: non-patent document 5).    Non-patent document 1: M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, pp. 245-246, 1990.    Non-patent document 2: X. Lin, J. Rajski, I. Pomeranz, S. M. Reddy, “On Static Test Compaction and Test Pattern Ordering for Scan Designs”, Proc. Intl. Test Conf., pp. 1088-1097, 2001.    Non-patent document 3: S. Kajihara, K. Ishida, and K. Miyase, “Test Vector Modification for Power Reduction during Scan Testing”, Proc. VLSI Test Symp., pp. 160-165, 2002.    Non-patent document 4: X. Wen, Y. Yamashita, S. Kajihara, L. Wang, K. K. Saluja, and K. Kinoshita, “On Low-Capture-Power Test Generation for Scan Testing”, Proc. VLSI Test Symp., pp. 265-270, 2005.    Non-patent document 5: R. Sankaralingam, R. Oruganti, and N. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation”, Proc. VLSI Test Symp., pp. 35-40, 2000.